The present invention is directed to semiconductor devices incorporating junctions of varying conductivity types and methods of making such devices. More specifically, the present invention relates to a bipolar junction transistor device and methods for fabricating integrated circuits incorporating such devices.
Enhancing semiconductor device performance and increasing device density (the number of devices per unit area) continue to be important objectives of the semiconductor industry. Device density is increased by making individual devices smaller and packing devices more compactly. But, as the device dimensions (also referred to as feature size or design rules) decrease, the methods for forming devices and their constituent elements must be adapted. For instance, production line feature sizes are currently in the range of 0.25 microns to 0.12 microns, with an inexorable trend toward small dimensions. However, as the device dimensions shrink, certain manufacturing limitations arise, especially with respect to the lithographic processes. In fact, current lithographic processes are nearing the point where it is not possible to accurately manufacture devices at the required minimal sizes demanded by today""s device users.
Currently most metal-oxide-semiconductor field effect transistors (MOSFETs) are formed in a lateral configuration with the current flowing parallel to the major plane of the substrate or body surface. As the size of these MOSFET devices decreases to achieve increased device density, the fabrication process becomes increasingly difficult. In particular, the lithographic process for creating the channel is problematic, as the wavelength of the radiation used to delineate an image in the lithographic pattern approaches the device dimensions. Therefore, for lateral MOSFETs, the gate length is approaching the point where it cannot be precisely controlled through the lithographic techniques.
Recent advances in packing density have resulted in several variations of a vertical MOSFET. In particular, the vertical device is described in Takato, H., et al., xe2x80x9cImpact of Surrounding Gates Transistor (SGT) for Ultra-High-Density LSI""s, IEEE Transactions on Electron Devices, Volume 38(3), pp. 573-577 (1991), has been proposed as an alternative to the planar MOSFET devices. Recently, there has been described a MOSFET characterized as a vertical replacement gate transistor. See Hergenrother, et al, xe2x80x9cThe Vertical-Replacement Gate (VRG) MOSFETxe2x80x9d: A 50-nm Vertical MOSFET with Lithography-Independent Gate Length,xe2x80x9d Technical Digest of the International Electron Devices Meeting, p. 75, 1999.
Generally, integrated circuits comprise a plurality of active devices, including MOSFETs, JFETs and bipolar junction transistors, as well as passive components such as resistors and capacitors. Commonly owned U.S. Pat. Nos. 6,027,975 and 6,197,641, which are hereby incorporated by reference, teach certain techniques for the fabrication of vertical replacement gate (VRG) MOSFETs. It is therefore advantageous to fabricate bipolar junction transistors (BJTs) using similar and compatible processing steps as those employed for the fabrication of MOSFETs to reduce integrated circuit fabrication costs.
An architecture and fabrication process is provided for fabricating BJTs using a process compatible with the fabrication of vertical MOSFETs.
According to one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first doped region formed therein. A plurality of semiconductor and insulating layers overlie the first doped region and a window or trench is formed in the plurality of layers. A second doped region of a different conductivity type than the first doped region is overlies the first doped region in the window. A third doped region, also in the window, overlies the second doped region, with a different conductivity type than the second doped region. The first region is a collector region of the BJT and the second region is the base. The third region is the emitter.
In an associated method of manufacture, an integrated circuit structure is fabricated by providing a semiconductor layer suitable for device formation and having a first surface formed along a first plane. A plurality of layers are formed thereover and a window is formed in the plurality of layers. For a BJT device, a first device region is formed in the semiconductor layer, where the device region is the collector. A base region is formed above the collector, and the emitter region formed above the base; both the base and emitter regions are formed in the window.
According to the present invention, BJTs and vertical MOSFETs can be fabricated in the same semiconductor substrate using compatible fabrication processes with minimal additional fabrication steps. That is, both devices are formed from a plurality of shared insulating and semiconductor layers, with certain of the active regions of each device formed in a window in the plurality of layers.